1. Field of the Invention
The present invention relates to systemic diagnostics for increasing wafer yield, and in particular to deriving metrics that facilitate calibration of design for manufacturability rules.
2. Related Art
One critical aspect of semiconductor manufacturing is ensuring good yield, i.e. the percentage of good chips on a wafer, when transitioning to a newer, smaller technology node. Unfortunately, current technology node transitions can result in yields being reduced even to 5%. Using feedback from running multiple wafers at a particular technology node, the yield can eventually be improved to a level consistent with commercial wafer production, e.g. 70%.
Improving the yield typically involves fabricating test chips on a wafer, each test chip including one library cell of each type, and then determining which library cells passed or failed. Using this information, “rules” can be generated for each technology node based on predetermined process conditions. These rules are developed by the wafer fabrication facility (i.e. a fab) and then provided to an integrated circuit (IC) design facility. Notably, this development requires multiple rounds of fabricating test chips, which is both resource and time intensive.
At this point, each designer can select which of the rules (e.g. hundreds or even thousands of rules) should be used for a new IC design. Specifically, some rules are mandatory whereas other rules are optional. Applying all of the rules to the IC design typically results in an undesirably large file size. Additionally, applying all of the rules may create an overly conservative IC design, which in turn may require a larger silicon footprint.
Therefore, although mandatory rules are followed, an IC design may use only a subset of the optional rules. Because of its complexity, a state of the art IC design may be divided into sections, each section of the IC design being assigned to a different designer or design team. Notably, each designer/design team may choose to apply any of the suggested rules. These mandatory and optional rules as well as other practices in the industry for improving yield have been called “Design For Manufacturability” (DFM).
FIG. 1 illustrates a simplified representation of an exemplary digital ASIC design flow including conventional DFM. At a high level, the process starts with the product idea (step 100) and is realized in an EDA software design process (step 110). When the design is finalized, it can be taped-out (event 140). After tape out, the fabrication process (step 150) and packaging and assembly processes (step 160) occur resulting, ultimately, in finished chips (result 170). The DFM rules 151, which are derived from analysis performed after fabrication, can be provided to designers for use in the EDA software design process. Applying DFM rules 151 provides DFM solutions 152, which can affect the EDA software process, tape-out, and fabrication. As describe above, the DFM rules 151, and thus DFM solutions 152, typically change based on multiple fabrications of test chips until final DFM rules 151 (bold line) are finalized, thereby producing optimized DFM solutions 152 (bold line).
Thus, the time to develop DFM rules 151 for a new technology node can significantly slow down the design flow. Therefore, it would be advantageous to develop rules that can leverage the design flow, e.g. in the EDA software process (step 110). Moreover, because optional rules have been subjectively selected for application, improvements in DFM have been inconsistent for different IC designs or even within the same IC design. Therefore, ensuring more consistent application of the rules during the EDA software process may also result in consistent improvements in DFM solutions.